For the past few decades, rigorous scaling methods have been driving the silicon (Si) complementary metal-oxide-semiconductor (CMOS) technology to enhance device performance, lower the power consumption and reduce cost per transistor. As the device dimension approaches the scaling limit, a paradigm shift has been actively explored in the semiconductor industry from dimensional scaling alone to materials innovation (i.e. “performance boosters”). One example is the integration of III-V compound materials, which have the necessary unique properties suitable for producing devices configured for future high speed and low power computation applications. Most III-V materials show 20-70 times higher electron mobility and approximately 20 times higher conductivity than those properties of Si. In addition, the feasibility of energy bandgap engineering of III-V materials enables fabrication of devices suitable for communications and optoelectronics. However, III-V materials per se cannot fully replace Si, because III-V substrates are very costly to manufacture, and also smaller in size due to their brittle mechanical properties (i.e. usually 200 mm). Therefore, small quantity of III-V materials has to be selectively integrated onto Si substrates to be compatible with existing mainstream CMOS manufacturing technologies. So to realize III-V materials integration on low cost and mechanically strong Si substrates, a number of research groups have been investigating III-V growth on Si substrates for optoelectronics and microelectronics applications.
In this respect, growing germanium (Ge) epitaxial layer on a Si substrate has attracted great attention among researchers, because of the potential applications in photonic and electronics devices. Perhaps most importantly, Ge is a group IV material, which is compatible with Si and thus may be processed in standard silicon manufacturing facilities. Another important application is that the Ge-on-Si substrate (Ge/Si) may also be used as a template for subsequent III-V compounds growth, since Ge is lattice-matched with gallium arsenide (GaAs). The desired Ge epitaxial film must have low defect density, in terms of threading dislocation density (TDD), and smooth surface with thin buffer layers.
One main challenge to produce high quality III-V materials on Si suitable for manufacturing compatibility with present CMOS technologies relates to the issue of significant lattice mismatch between the two materials (e.g. the mismatch is about 4.1% in the case of GaAs). To resolve the issue, Ge, which has a lattice constant that is perfectly matched to GaAs (i.e. 0.07% at 300 K) and has superior electron and hole mobility compared to Si, can first be grown on Si to provide a buffer layer for integration and fabrication of GaAs-based devices on Si substrate. Another possible solution is to form a germanium-on-insulator (GOI) substrate for the same application described above. Besides acting as a “passive” buffer layer, Ge on Si, or GOI substrates (with no III-V layers) may further have potential applications in advanced CMOS circuit and photonics.
But it is also to be appreciated that the challenge in growing Ge on Si falls on the approximately 4% lattice mismatch between Si and Ge, which may result in a high defect density with rough surface. A known method to address this problem is to grow a SiGe graded buffer with variable composition, and smoothen the surface of the graded buffer via chemical mechanical polishing (CMP) at a composition of Si0.5Ge0.5. Through this method, a TDD of about 105/cm2 can be achieved, but it however requires a 10 μm thick graded SiGe buffer layer. Such thickness is practically obtainable using typical high-temperature chemical vapour deposition (CVD) processes resulting in μm/min growth rates. However, sometimes it may be desirable to have thinner initial layers for some applications, e.g. laser, photovoltaic, and etc.
A two-step growth approach using various types of CVD tools is another known approach. This approach includes a low temperature (i.e. 330-400° C.) growth step that is followed by a high temperature (i.e. 600-850° C.) Ge growth. The TDD is then greatly reduced by carrying out post-growth annealing or thermal cyclic annealing. Unfortunately, this method still results in the Ge/Si having a much higher TDD of greater than 107/cm2. Undesirably, the high TDD level is anticipated to degrade any subsequent III-V materials integration, and may also consequently lead to device failure later on in usage.
Another approach to reduce the TDD is through annealing the GOI substrate which is fabricated through bonding and layer transferring a Ge epilayer that is grown using the two-step approach. Using this method, an etch-pit density (EPD) of lesser than 106/cm2 may be obtained.
One object of the present invention is therefore to address at least one of the problems of the prior art and/or to provide a choice that is useful in the art.